As data processing system bus speeds increase there has been a movement from asynchronous to synchronous memory interfaces. This is especially true for dynamic random access memories (DRAM), due to their relatively slow access speeds. A synchronous interface allows for a significantly faster interface. One speed disadvantage of an asynchronous memory system is that transactions are initiated and completed atomically. Therefore each transaction must be completed before the next transaction is begun. Synchronous memory interfaces allow various stages of the transaction to be pipelined, where requests to the memory and responses from the memory are overlapped.
Although synchronous memories provide speed advantages, they also create unique problems with respect to timing and clocking. This becomes a special burden for a system designer trying to implement a cost effective solution while at the same time meeting design specifications for the devices in a system. Hold times may be very difficult to meet, both from the perspective of the memory and the perspective of a processor. In the microcontroller environment, this can be even more difficult if bus clocks are derived from input signals of different frequencies or large skews with respect to the input clock. Bus specifications may be related to output clocks, and so a simple clock tree arrangement will not guarantee synchronous clocks.
FIG. 1 is a prior art timing diagram of an interface between a micro controller and a synchronous memory. Three signals are illustrated: clock out, SDRAM control out, and SDRAM clock. The clock out signal is generated by the data processing system. The bus specifications are defined with respect to this clock out signal. The SDRAM control out signal is generated by the data processing system and is recognized by a synchronous (SDRAM) memory. The SDRAM clock is the input clock to the synchronous DRAM (SDRAM) memory. Two time intervals are illustrated in FIG. 1. The first period is the output hold time for the data processing system. This is the minimum amount of time between a rising clock edge transition and the transition of an output to the memory. The other time period illustrated is the DRAM input hold time requirement. This is the minimum amount of time that a signal must be held after the DRAM input clock rising edge transition to be successfully recognized. In this illustration, the output hold time is two nanoseconds and the DRAM input hold time requirement is one nanosecond. The result is that the difference, one nanosecond, is the maximum skew allowed between the clock out of the data processing system and the clock into the SDRAM. This minimum skew requirement greatly increases the design complexity required in designing a system using synchronous DRAM (SDRAM). It should be noted that there is a similar requirement for data returning to the micro controller from a synchronous memory.
Prior to this invention, the problem has been solved with relatively expensive external hardware, such as a phased locked loop (PLL), and rigorous circuit board design to tightly control the skew of the clocks.
It would therefore be advantageous to provide a system solution which would allow the setup and hold time requirements of the devices within the system to easily be achieved without rigorous control of the clocks. This would significantly simplify the system design of an interface to a synchronous memory.